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PRELIMINARY
W161
133-MHz Spread Spectrum FTG for Pentium(R) II Platforms
Features
* Maximized EMI Suppression using Cypress's Spread Spectrum Technology * Three copies of CPU outputs at 100 or 133 MHz * Three copies of 66-MHz output at 3.3V * Ten copies of PCI clocks at 33 MHz, 3.3V * Two copies of 14.318-MHz reference output at 3.3V * One copy of 48-MHz USB clock * One copy of CPU-divide-by-2 output as reference input to Direct RambusTM Clock Generator (Cypress W134) * Available in 48-pin SSOP (300 mils) Spread Spectrum Modulation:..................................... -0.5% CPU to 3V66 Output Offset: ............. 0.0-1.5 ns (CPU leads) 3V66 to PCI Output Offset:.............. 1.5-3.0 ns (3V66 leads) CPU to IOAPIC Output Offset: ......... 1.5-4.0 ns (CPU leads) Table 1. Pin Selectable Frequency SEL133/100# SEL1 SEL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Function All outputs Three-State (Reserved) Active 100-MHz, 48-MHz PLL inactive Active 100-MHz, 48-MHz PLL active Test Mode (Reserved) Active 133-MHz, 48-MHz PLL inactive Active 133-MHz, 48-MHz PLL active
Key Specifications
Supply Voltages: ...................................... VDDQ2 = 2.5V5% VDDQ3 = 3.3V5% CPU, CPUdiv2 Output Jitter:....................................... 250 ps CPU, CPUdiv2 Output Skew: ...................................... 175 ps IOAPIC, 3V66 Output Skew: ....................................... 250 ps PCI0:9 Output Skew: .................................................. 500 ps Duty Cycle: ................................................................... 45/55
Block Diagram
X1 X2
Pin Configuration [1]
XTAL OSC
2 REF_[0:1]
3 CPU_[0:2]
SPREAD# SEL0 SEL1 SEL133/100#
/2
CPUdiv2
PLL 1
3 /2//1.5 3V66_[0:2]
9 PWRDWN# /2 PCI_[0:9]
Power Down Logic
/2
IOAPIC
REF0 REF1 VDDQ3 X1 X2 GND PCI0 PCI1 VDDQ3 PCI2 PCI3 PCI4 PCI5 GND PCI6 PCI7 VDDQ3 PCI8 PCI9 GND 3V66_0 3V66_1 3V66_2 VDDQ3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND VDDQ2 IOAPIC GND VDDQ2 CPUdiv2 GND VDDQ2 CPU2 GND VDDQ2 CPU1 CPU0 GND VDDQ3 GND PWRDWN#* SPREAD#* SEL1* SEL0* VDDQ3 48MHz GND SEL133/100#
Note: 1. Internal 250-k pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
W161
Three-state Logic
PLL2
48MHz
Pentium is a registered trademark of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 October 13, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPU0:2 PCI0:9 Pin No. 36, 37, 40 7, 8, 10, 11, 12, 13, 15, 16, 18, 19 43 Pin Type O O Pin Description
W161
CPU Clock Outputs 0 through 2: CPU clock outputs. Their output voltage swing is controlled by voltage applied to VDDQ2. PCI Clock Outputs 0 through 9: Output voltage swing is controlled by voltage applied to VDDQ3. CPU-Divide-By-2 Output: This serves as a reference input signal for Direct Rambus Clock Generator (Cypress W134). The output voltage is determined by VDDQ2. 66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by voltage applied to VDDQ3. I/O APIC Clock Output: Provides an output synchronous to CPU clock. See Table 1 for their relation to other system clock outputs. 48-MHz Output: Fixed clock output at 48 MHz. Spread Spectrum Enable: This input enables spread spectrum modulation on the PLL1 generated frequency outputs of the W161. Modulation range is -0.5%. Power Down Control Fixed 14.318-MHz Output 0 and 1: Output voltage swing is controlled by voltage applied to VDDQ3. Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting clock output modes. As shown in Table 1. Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output frequency as shown in Table 1. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Connected to 2.5V power supply. Power Connection: Connected to 3.3V power supply. Ground Connection: Connect all ground pins to the common system ground plane.
CPUdiv2
O
3V66_0:2 IOAPIC 48 MHz SPREAD#
21, 22, 23 46 27 31
O O O I
PWRDWN# REF0:1 SEL0:1 SEL133/100# X1
32 1, 2 29, 30 25 4
I I I I I
X2 VDDQ2 VDDQ3 GND
5 38, 41, 44, 47 3, 9, 17, 24, 28, 34 6, 14, 20, 26, 33, 35, 39, 42, 45, 48
I P P G
Overview
The W161, a motherboard clock synthesizer, provides 2.5V CPU clock outputs for advanced CPU and a CPU-divide-by-2 reference frequency for Direct Rambus Clock Generator (such Cypress W134) interface. Fixed output frequencies are provided for other system functions. CPU Frequency Selection CPU frequency is selected with input pins 25, 29, and 30 (SEL133/100#, SEL0, and SEL1, respectively). Refer to Table 1 for details. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serial terminated clock lines. The W161 outputs are CMOS-type, which provide rail-to-rail output swing.
Crystal Oscillator The W161 requires one input reference clock to synthesize all output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by the internal crystal oscillator. When using an external clock signal, pin X1 is used as the clock input and pin X2 is left open. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The W161 incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 18 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of 18 pF should be used. This will typically yield reference frequency accuracies within 100 ppm.
2
PRELIMINARY
Spread Spectrum Feature
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F)
W161
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is -0.5% downspread. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices.
EMI Reduction
Spread Spectrum Enabled NonSpread Spectrum
Figure 1. Typical Clock and SSFTG Comparison
100% 80% 60% 40% 20% 0% -20% -40% -60% -80% -100%
Frequency Shift
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
Time
Figure 2. Typical Modulation Profile
3
100%
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
W161
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV
Parameter VDD, VIN TSTG TA TB ESDPROT
Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%
Parameter Supply Current IDD-3.3V IDD-2.5 VIL VIH IIL IIH IIL IIH Combined 3.3V Supply Current Combined 2.5V Supply Current Input Low Voltage Input High Voltage Input Low Current[3] Input High Current
[3]
Description
Test Condition CPU0:3 =133 MHz[2] CPU0:3 =133 MHz
[2]
Min.
Typ.
Max. 160 90
Unit mA mA V V A A A A Unit mV V mA mA Unit mV V mA mA Unit mV V mA mA
Logic Inputs (All referenced to VDDQ3 = 3.3V) GND - 0.3 2.0 0.8 VDD + 0.3 -25 10 -5 5 Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.25V VOH = 1.25V Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V 3.1 70 65 100 95 145 135 3.1 45 45 Min. 65 65 Typ. 100 100 Max. 50 2.2 45 45 Min. 65 65 Typ. 100 100 Max. 50 Min. Typ. Max. 50
[3]
Input Low Current, SEL133/100#[3] Input High Current, SEL133/100#
Clock Outputs CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2) VOL VOH IOL IOH Output Low Voltage Output High Voltage Output Low Current Output High Current
48MHz, REF (Referenced to VDDQ3) Output Low Voltage VOL VOH IOL IOH VOL VOH IOL IOH Output High Voltage Output Low Current Output High Current Output Low Voltage Output High Voltage Output Low Current Output High Current
PCI, 3V66 (Referenced to VDDQ3)
Notes: 2. All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 3. W161 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
4
PRELIMINARY
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5% (continued)
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input threshold Voltage[4] Load Capacitance, Imposed on External Crystal[5] X1 Input Capacitance[6] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 1.65 18 28 5 6 7 Description Test Condition Min. Typ. Max.
W161
Unit V pF pF pF pF nH
Pin Capacitance/Inductance
3.3V AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%,VDDQ2 = 2.5V 5%, fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[7] 3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF) Parameter f tR tF tD fST Description Frequency Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Note 8 Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 1 1 45 Test Condition/Comments Min. Typ. 66.6 4 4 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
Notes: 4. X1 input threshold voltage (typical) is VDD/2. 5. The W161 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 7. Period, jitter, offset, and skew measured on rising edge at 1.5V. 8. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
5
PRELIMINARY
PCI Clock Outputs, PCI0:9 (Lump Capacitance Test Load = 30 pF Parameter tP tH tL tR tF tD tJC tSK tO fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew 3V66 to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V
[9]
W161
Min. 30 12 12 1 1 45
Typ.
Max.
Unit ns ns ns
Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V. Covers all 3V66/PCI outputs. Measured on rising edge at 1.5V. 3V66 leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value.
4 4 55 500 500
V/ns V/ns % ps ps ns ms
1.5
3 3
Zo
15
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 V/ns V/ns % ms Max. Unit
Zo
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
Note: 9. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
6
PRELIMINARY
2.5V AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, V DDQ2= 2.5V5% fXTL = 14.31818 MHz Spread Spectrum function turned off
W161
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[10] CPU Clock Outputs, CPU0:2 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 7.5 1.87 1.67 1 1 45 4 4 55 250 7.65 CPU = 100 MHz Typ. Max. Unit 10.2 ns ns ns 4 4 55 250 V/ns V/ns % ps 10 3.0 2.8 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start)
175 3
175 3
ps ms
CPUdiv2 Clock Outputs, CPUdiv2 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 15 5.25 5.05 1 1 45 4 4 55 250 15.3 CPU = 100 MHz Typ. Max. 20.4 Unit ns ns ns 4 4 55 250 V/ns V/ns % ps 20 7.5 7.3 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
20
Note: 10. Period, Jitter, offset. and skew measured on rising edge at 1.25V.
7
PRELIMINARY
IOAPIC Clock Output, IOAPIC (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Note 11 Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 1 1 45 Test Condition/Comments Min Typ 16.67 4 4 55 3 Max
W161
Unit MHz V/ns V/ns % ms
Zo
Note: 11. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
Ordering Information
Ordering Code W161 Document #: 38-00817 Package Name H Package Type 48-pin SSOP (300 mils)
8
PRELIMINARY
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
W161
Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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